The present embodiments relate to integrated circuits and, more particularly, to dynamic clock-data phase alignment in a source-synchronous interface circuit.
Signal transmission and reception is the basis for communication between circuits within electronic devices as well as between circuits within different electronic devices. However, when building high-performance products, system developers face significant challenges in maintaining the precise timing and signal integrity required to reliably sustain high data rates. Differential signaling standards like low voltage differential signaling (LVDS) aid in this effort by providing common mode rejection, which greatly reduces the effects of electrical noise.
Clock-data recovery (CDR) transceiver implementations combine the clock and data into a single signal, thus ensuring simultaneous arrival at their destination. However, a number of interface standards such as DDR memory, HyperTransport buses, and the System Packet Interface (SPI) 4.2 standard are source-synchronous. Those source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal.
On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. For example, edge-aligned clock and data signals must be phase shifted relative to each other by 90 degrees such that the edge of the clock signal is aligned with the center of the data signal, thereby enabling the storage of the data signal in a storage circuit that is triggered by an edge of the clock signal.
Dynamic phase alignment (DPA) technology has been developed to address the phase alignment in interfaces that require data ranges above 700 megabits per second (Mbps). The goal of dynamic phase alignment (DPA) is to allow devices to actively respond to changes in skew between the transmitted clock and data signals. Integrated circuits that are equipped with DPA continuously check the incoming data signal and adjust the phase of the clock signal to align with it. Several industry standards responsible for defining source synchronous interfaces, including System Packet Interface (SPI) 4.2, have recognized the value of DPA, and have included or recommended it in their specifications.